Melola Discovery

← Melola Discovery

Open access Jurnal SINTA 1

Field programmable gate array implementation frameworks of a variable-length pseudorandom pattern generator

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 15 No. 1 (2025)

DOI
10.11591/ijece.v15i1.pp186-195
ISSN
2722-2578, 2088-8708
Published
2025-02-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

A pseudorandom pattern generator produces sequences similar to true random sequences. A variable length pseudo-random pattern generator (PRPG), which can be used as a pattern generator for various applications like built-in self-test (BIST) or cryptography, is proposed in this paper. Our work is based on a linear feedback shift register circuit platform. The proposed design can generate patterns corresponding to different characteristic polynomials of any given polynomial degree. These characteristic polynomials are integrated into the linear feedback shift register circuit by providing an option to select the feedback paths of any of these polynomials. This paper implements and evaluates the proposed design for primitive and non-primitive characteristic polynomials of degrees 3 to 15. The circuit generates output patterns of different periods based on user inputs. Compared to other pseudorandom pattern generator circuits, the proposed circuit can generate a large set of patterns and consumes less power. Adequate results from the experiments demonstrate the functionalities and performance of the proposed pattern generator from degrees 3 to 15. The proposed circuit generates pseudorandom patterns that can be used not only for built-in self-test but also for cryptography and wireless communication applications.

Collaboration network of the authors

3 authors · 2 co-authorship links

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Amrita Vishwa Vidyapeetham
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Devika Kalathil NandalalAmrita Vishwa Vidyapeetham1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Field programmable gate array implementation frameworks of a variable-length pseudorandom pattern generator</dc:title><dc:creator>Somanathan, Geethu Remadevi</dc:creator><dc:creator>Bhakthavatchalu, Ramesh</dc:creator><dc:description>&lt;jats:p&gt;A pseudorandom pattern generator produces sequences similar to true random sequences. A variable length pseudo-random pattern generator (PRPG), which can be used as a pattern generator for various applications like built-in self-test (BIST) or cryptography, is proposed in this paper. Our work is based on a linear feedback shift register circuit platform. The proposed design can generate patterns corresponding to different characteristic polynomials of any given polynomial degree. These characteristic polynomials are integrated into the linear feedback shift register circuit by providing an option to select the feedback paths of any of these polynomials. This paper implements and evaluates the proposed design for primitive and non-primitive characteristic polynomials of degrees 3 to 15. The circuit generates output patterns of different periods based on user inputs. Compared to other pseudorandom pattern generator circuits, the proposed circuit can generate a large set of patterns and consumes less power. Adequate results from the experiments demonstrate the functionalities and performance of the proposed pattern generator from degrees 3 to 15. The proposed circuit generates pseudorandom patterns that can be used not only for built-in self-test but also for cryptography and wireless communication applications.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2025-02-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v15i1.pp186-195</dc:identifier><dc:identifier>10.11591/ijece.v15i1.pp186-195</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 15 No 1 (2025); 186</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>https://ijece.iaescore.com/index.php/IJECE/article/viewFile/35030/17953</dc:relation><dc:rights>http://creativecommons.org/licenses/by-sa/4.0</dc:rights></oai_dc:dc>