Design of low power complementary metal-oxide semiconductor static random-access memory cell for embedded memories at three different technology nodes

Abstract

In this work, the complementary metal-oxide semiconductor (CMOS) static random-access memory (SRAM) cell is proposed using a hybrid model. It is designed by combining two different methods and simulated at different technologies which are 180, 90, and 45 nm. The proposed hybrid model SRAM cell has less power consumption. The power consumption results of the hybrid model SRAM cell are contrasted with the 6T CMOS SRAM, Stacked SRAM cell, and 8T SRAM cell at 180, 90, and 45 nm. Tanner tool was used for designing and simulating these different SRAM cell topologies at 180, 90, and 45 nm technology nodes. S-edit is used for designing circuit diagrams, T-edit is used for simulating spice net lists and W-edit is used for observing waveforms in Tanner tool. The hybrid SRAM cell at 45 nm got better power consumption results than other SRAM cell topologies at different technology nodes.