Efficient power optimized very-large-scale integration architecture of proportionate least mean square adaptive filter

Abstract

The focus on power optimization in embedded systems is especially important for embedded applications since it has brought in many methods and factors that are necessary for developing systems that are both power- and area-efficient. In contrast to the current delayed wavelet μ-law proportionate least mean square (DWMPLMS) and delayed least mean square (DLMS) algorithms, this work offers the development of adaptive filters based on the least mean square (LMS) method, which improves power and timing performance. In order to improve area and time efficiency, the proportionate least mean square (PLMS) algorithm's architecture has been modified to remove delay, add a proportionate gain block, design for a fixed length, include an approximate multiplier block, and swap out standard blocks for floating-point adder and divider blocks. According to a power and temporal comparison with the DWMPLMS and DLMS algorithms, field-programmable gate array (FPGA) synthesis reduces power usage by 95% for a 32-bit filter length in PLMS when compared to the above methods.