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A new multiplier less memcapacitor emulator with non-linear applications

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 16 No. 3 (2026)

DOI
10.11591/ijece.v16i3.pp1132-1147
ISSN
2722-2578, 2088-8708
Published
2026-06-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

This study describes a memcapacitor emulator without a multiplier that make use of second-generation current conveyor (CCII), operational trans-conductance amplifier (OTA) and the fewest possible passive components. The proposed memcapacitor is proved mathematically and verified using several simulation approaches, such as process corner, non-volatile and hysteresis analysis. Also, provided the layout of CCII and OTA as well. The standard CMOS 90 nm technology is used in the Cadence Virtuoso tool to simulate the proposed memcapacitor emulator. This article also includes the use of memcapacitor emulator in the applications of R-C frequency selective network as well as adaptable neuromorphic structure. To investigate the experimental outcomes, an experimental setup was constructed with commercially available integrated circuits (ICs) CCII’s AD844AN and OTA’s CA3080EZ.

Collaboration network of the authors

3 authors · 3 co-authorship links

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  • JSS Science and Technology University
  • Affiliation unknown
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  • Same organisation
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Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
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