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Design and Performance Analysis of a Fast 4-Way Set Associative Cache Controller using Tree Pseudo Least Recently Used Algorithm

Indonesian Journal of Electical Engineering and Informatics (IJEEI) · Vol. 11 No. 4 (2023) · hlm. 1051–1063

DOI
10.52549/.v11i4.5014
ISSN
2089-3272, 2089-3272
Terbit
2023-12-24
Penerbit
IAES Indonesian Section
Bahasa
en

Abstrak

In the realm of modern computing, cache memory serves as an essential intermediary, mitigating the speed disparity between rapid processors and slower main memory. Central to this study is the development of an innovative cache controller for a 4-way set associative cache, meticulously crafted using VHDL and structured as a Finite State Machine. This controller efficiently oversees a cache of 256 bytes, with each block encompassing 128 bits or 16 bytes, organized into four sets containing four lines each. A key feature of this design is the incorporation of the Tree Pseudo Least Recently Used (PLRU) algorithm for cache replacement, a strategic choice aimed at optimizing cache performance. The effectiveness of this controller was rigorously evaluated using ModelSim, which generated a comprehensive timing diagram to validate the design's functionality, especially when integrated with a segmented main memory of four 1KB banks. The results from this evaluation were promising, showcasing precise logic outputs within the timing diagram. Operational efficiency was evidenced by the controller's swift processing speeds: read hits were completed in a mere three cycles, read misses in five and a half cycles, and both write hits and misses in three and a half cycles. These findings highlight the controller's capability to enhance cache memory efficiency, striking a balance between the complexities of set-associative mapping and the need for optimized performance in contemporary computing systems. This study not only demonstrates the potential of the proposed cache controller design in bridging the processor-memory speed gap but also contributes significantly to the field of cache memory management by offering a viable solution to the challenges posed by traditional cache configurations.

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  • International Islamic University Malaysia
  • Yogyakarta State University
  • Syarif Hidayatullah State Islamic University Jakarta
  • Universitas Gadjah Mada
  • University of Kuala Lumpur
  • University of Indonesia
  • International Centre for Education in Islamic Finance
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Rekan penulisOrganisasiArtikel bersama
Ali SophianInternational Islamic University Malaysia8
Arselan AshrafInternational Islamic University Malaysia8
Mohamed Hadi HabaebiInternational Islamic University Malaysia7
Siti Hajar YusoffInternational Islamic University Malaysia6
Aris NasuhaYogyakarta State University5
Anggun WinursitoYogyakarta State University5
Hasmah MansorInternational Islamic University Malaysia4
Malik Arman MorshidiInternational Islamic University Malaysia4
Ardy Seto PriambodoYogyakarta State University4
Rashidah Funke OlanrewajuInternational Islamic University Malaysia3
Suriza Ahmad ZabidiInternational Islamic University Malaysia3
Noreha Abdul MalikInternational Islamic University Malaysia2
Diyah PutrianiUniversitas Gadjah Mada2
Gairuzazmi Mat GhaniInternational Islamic University Malaysia2
Amart SulongInternational Islamic University Malaysia2
Othman Omran KhalifaInternational Islamic University Malaysia2
Hassan DaoUniversity of Kuala Lumpur2
Abdul MutholibInternational Islamic University Malaysia2
Intan Rahmithul Husna YaldiInternational Islamic University Malaysia2
Yasmin Mahira Saiful MunirInternational Islamic University Malaysia2
Tika ArundinaUniversity of Indonesia2
Mohd Azmi OmarInternational Centre for Education in Islamic Finance2
Nur Atikah Muhamat SalehInternational Islamic University Malaysia2
Mir Suhail AlamInternational Islamic University Malaysia2
Mohd Shahrin Abu HanifahInternational Islamic University Malaysia2
W. IdrisInternational Islamic University Malaysia1
Siti Noorjannah IbrahimInternational Islamic University Malaysia1
Abd Rahman AhlanAfiliasi tidak diketahui1
A’ang SubiyaktoSyarif Hidayatullah State Islamic University Jakarta1
Husni Teja SukmanaSyarif Hidayatullah State Islamic University Jakarta1
Didik HariyantoYogyakarta State University1
Arif Ainur RafiqPoliteknik Negeri Cilacap1
Nguyen Vu QuynhLac Hong University1
Suprapto SupraptoYogyakarta State University1
Muslikhin MuslikhinYogyakarta State University1

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Sumber metadata: OAI-PMH (metadata jurnal) http://section.iaesonline.com/index.php/IJEEI/oai, pertama di-harvest 8 Nov 2026, terakhir terlihat 8 Nov 2026.
Metadata asli (oai_dc) 
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	<dc:title xml:lang="en">Design and Performance Analysis of a Fast 4-Way Set Associative Cache Controller using Tree Pseudo Least Recently Used Algorithm</dc:title>
	<dc:creator xml:lang="en">Hazlan, Mohamed Alfian Al-Zikry</dc:creator>
	<dc:creator xml:lang="en">Gunawan, Teddy Surya</dc:creator>
	<dc:creator xml:lang="en">Yaacob, Mashkuri</dc:creator>
	<dc:creator xml:lang="en">Kartiwi, Mira</dc:creator>
	<dc:creator xml:lang="en">Arifin, Fatchul</dc:creator>
	<dc:subject xml:lang="en">Cache controller</dc:subject>
	<dc:subject xml:lang="en">VHDL-designed</dc:subject>
	<dc:subject xml:lang="en">Finite State Machine</dc:subject>
	<dc:subject xml:lang="en">4-way set associative cache</dc:subject>
	<dc:subject xml:lang="en">Tree PLRU algorithm</dc:subject>
	<dc:description xml:lang="en">In the realm of modern computing, cache memory serves as an essential intermediary, mitigating the speed disparity between rapid processors and slower main memory. Central to this study is the development of an innovative cache controller for a 4-way set associative cache, meticulously crafted using VHDL and structured as a Finite State Machine. This controller efficiently oversees a cache of 256 bytes, with each block encompassing 128 bits or 16 bytes, organized into four sets containing four lines each. A key feature of this design is the incorporation of the Tree Pseudo Least Recently Used (PLRU) algorithm for cache replacement, a strategic choice aimed at optimizing cache performance. The effectiveness of this controller was rigorously evaluated using ModelSim, which generated a comprehensive timing diagram to validate the design's functionality, especially when integrated with a segmented main memory of four 1KB banks. The results from this evaluation were promising, showcasing precise logic outputs within the timing diagram. Operational efficiency was evidenced by the controller's swift processing speeds: read hits were completed in a mere three cycles, read misses in five and a half cycles, and both write hits and misses in three and a half cycles. These findings highlight the controller's capability to enhance cache memory efficiency, striking a balance between the complexities of set-associative mapping and the need for optimized performance in contemporary computing systems. This study not only demonstrates the potential of the proposed cache controller design in bridging the processor-memory speed gap but also contributes significantly to the field of cache memory management by offering a viable solution to the challenges posed by traditional cache configurations.</dc:description>
	<dc:publisher xml:lang="en">IAES Indonesian Section</dc:publisher>
	<dc:date>2023-12-24</dc:date>
	<dc:type>info:eu-repo/semantics/article</dc:type>
	<dc:type>info:eu-repo/semantics/publishedVersion</dc:type>
	<dc:format>application/pdf</dc:format>
	<dc:identifier>https://section.iaesonline.com/index.php/IJEEI/article/view/5014</dc:identifier>
	<dc:identifier>10.52549/.v11i4.5014</dc:identifier>
	<dc:source xml:lang="en">Indonesian Journal of Electrical Engineering and Informatics (IJEEI); Vol. 11 No. 4: December 2023; 1051-1063</dc:source>
	<dc:source>2089-3272</dc:source>
	<dc:source>2089-3272</dc:source>
	<dc:language>en</dc:language>
	<dc:relation>https://section.iaesonline.com/index.php/IJEEI/article/view/5014/880</dc:relation>
</oai_dc:dc>