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INVESTIGATION OF FLIP-FLOP PERFORMANCE ON DIFFERENT TYPE AND ARCHITECTURE IN SHIFT REGISTER WITH PARALLEL LOAD APPLICATIONS

Jurnal Ilmu Komputer dan Informasi (JIKI) · Vol. 8 No. 2 (2015) · pp. 83–91

DOI
10.21609/jiki.v8i2.306
ISSN
2502-9274, 2088-7051
Published
2015-08-27
Publisher
Faculty of Computer Science - Universitas Indonesia
Language
eng

Abstract

Register is one of the computer components that have a key role in computer organisation. Every computer contains millions of registers that are manifested by flip-flop. This research focuses on the investigation of flip-flop performance based on its type (D, T, S-R, and J-K) and architecture (structural, behavioural, and hybrid). Each type of flip-flop on each architecture would be tested in different bit of shift register with parallel load applications. The experiment criteria that will be assessed are power consumption, resources required, memory required, latency, and efficiency. Based on the experiment, it could be shown that D flip-flop and hybrid architecture showed the best performance in required memory, latency, power consumption, and efficiency. In addition, the experiment results showed that the greater the register number, the less efficient the system would be.

Keywords

Collaboration network of the authors

16 authors · 43 co-authorship links · 16 across different organisations

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  • University of Indonesia
  • KTH Royal Institute of Technology
  • Pelita Harapan University
  • University of Edinburgh
  • Utah State University
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
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Co-authorOrganisationJoint articles
Novian HabibieUniversity of Indonesia4
Benny HardjonoPelita Harapan University3
Grafika JatiUniversity of Indonesia3
Dwi Marhaendro Jati PurnomoUniversity of Indonesia2
Muhammad Febrian RachmadiUniversity of Edinburgh1
Ahmad ArinaldiUniversity of Indonesia1
Dwi Teguh PriyantiniUniversity of Indonesia1
Andreas FebrianUtah State University1
Hanif Arief WisesaUniversity of Indonesia1
Satria Bagus WicaksonoAffiliation unknown1
Puteri Khatya FahiraUniversity of Indonesia1
Rafif Naufal RahmadikaAffiliation unknown1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

Metadata source: OAI-PMH (metadata jurnal) https://jiki.cs.ui.ac.id/index.php/jiki/oai, first harvested 26 Okt 2026, last seen 26 Okt 2026.
Original metadata (oai_dc) 
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	<dc:title xml:lang="en-US">INVESTIGATION OF FLIP-FLOP PERFORMANCE ON DIFFERENT TYPE AND ARCHITECTURE IN SHIFT REGISTER WITH PARALLEL LOAD APPLICATIONS</dc:title>
	<dc:creator>Purnomo, Dwi</dc:creator>
	<dc:creator>Alhamidi, Machmud Roby</dc:creator>
	<dc:creator>Wibisono, Ari</dc:creator>
	<dc:creator>Tawakal, Muhammad Iqbal</dc:creator>
	<dc:subject xml:lang="en-US">Memory</dc:subject>
	<dc:subject xml:lang="en-US">flip-flop</dc:subject>
	<dc:subject xml:lang="en-US">performance</dc:subject>
	<dc:subject xml:lang="en-US">type and architecture</dc:subject>
	<dc:subject xml:lang="en-US">performance criteria</dc:subject>
	<dc:description xml:lang="en-US">Register is one of the computer components that have a key role in computer organisation. Every computer contains millions of registers that are manifested by flip-flop. This research focuses on the investigation of flip-flop performance based on its type (D, T, S-R, and J-K) and architecture (structural, behavioural, and hybrid). Each type of flip-flop on each architecture would be tested in different bit of shift register with parallel load applications. The experiment criteria that will be assessed are power consumption, resources required, memory required, latency, and efficiency. Based on the experiment, it could be shown that D flip-flop and hybrid architecture showed the best performance in required memory, latency, power consumption, and efficiency. In addition, the experiment results showed that the greater the register number, the less efficient the system would be.</dc:description>
	<dc:publisher xml:lang="en-US">Faculty of Computer Science  - Universitas Indonesia</dc:publisher>
	<dc:date>2015-08-27</dc:date>
	<dc:type>info:eu-repo/semantics/article</dc:type>
	<dc:type>info:eu-repo/semantics/publishedVersion</dc:type>
	<dc:format>application/pdf</dc:format>
	<dc:identifier>https://jiki.cs.ui.ac.id/index.php/jiki/article/view/306</dc:identifier>
	<dc:identifier>10.21609/jiki.v8i2.306</dc:identifier>
	<dc:source xml:lang="en-US">Jurnal Ilmu Komputer dan Informasi; Vol. 8 No. 2 (2015): Jurnal Ilmu Komputer dan Informasi (Journal of Computer Science and Information); 83- 91</dc:source>
	<dc:source>2502-9274</dc:source>
	<dc:source>2088-7051</dc:source>
	<dc:source>10.21609/jiki.v8i2</dc:source>
	<dc:language>eng</dc:language>
	<dc:relation>https://jiki.cs.ui.ac.id/index.php/jiki/article/view/306/341</dc:relation>
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