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Analysis of Binary DC Source Reduced Switch 7-level Inverter

International Journal of Power Electronics and Drive Systems · Vol. 6 No. 1 (2015) · hlm. 70–76

DOI
10.11591/ijpeds.v6.i1.pp70-76
ISSN
2722-256X, 2088-8694
Terbit
2015-03-01
Penerbit
Institute of Advanced Engineering and Science
Bahasa
eng
Lisensi
creativecommons.org/licenses/by-sa/4.0

Abstrak

This paper proposes a binary DC source reduced switch 7-level inverter. Binary DC source reduced switch inverter is triggered by the Unipolar PWM strategy having sinusoidal and trapezoidal reference with triangular carriers. These Pulse Width Modulating (PWM) strategies include Phase Disposition (PD), Alternate Phase Opposition Disposition (APOD), Carrier Overlapping (CO). Performance factors like Total Harmonic Distortion (THD), VRMS (fundamental) and crest factor are evaluated for various modulation indices. Simulations were performed using MATLAB-SIMULINK. It is observed that UPDPWM strategy with trapezoidal reference provides output with relatively low distortion and UCOPWM strategy with trapezoidal reference provides relatively higher fundamental RMS output voltage.

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26 penulis · 63 tautan kepenulisan bersama · 37 lintas organisasi

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  • Arunai Engineering College
  • Annamalai University
  • Mohan Babu University
  • University of Moratuwa
  • Sri Chandrasekharendra Saraswathi Viswa Mahavidyalaya
  • Anna University, Chennai
  • Bahir Dar University
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Rekan penulisOrganisasiArtikel bersama
V. SaravananArunai Engineering College5
K. VenkatachalamArunai Engineering College3
K.T.M.U. HemapalaUniversity of Moratuwa3
V. BalajiBahir Dar University3
V. SaravananArunai Engineering College2
M.A.K BorelessaUniversity of Moratuwa2
M. AravindanSri Chandrasekharendra Saraswathi Viswa Mahavidyalaya2
S.P. NatarajanAnnamalai University2
Chinnapettai Ramalingam BalamuruganKarpagam Academy of Higher Education2
K. M. VenkatachalamArunai Engineering College1
M. A. K. BorelessaAfiliasi tidak diketahui1
M. AravindanSri Chandrasekharendra Saraswathi Viswa Mahavidyalaya1
M. SabithaAnna University, Chennai1
V. BinduAnna University, Chennai1
T. Nageswara PrasadMohan Babu University1
S. PrabhuMohan Babu University1
N. AshokkumarMohan Babu University1
N. M. G. KumarAfiliasi tidak diketahui1
Natarajan PrabaharanSASTRA University1
T. S. AnandhiAnnamalai University1
K. VenkataramananArunai Engineering College1
Thangavel Swaminathan SivakumaranArunai Engineering College1
T.S. AnandhiAnnamalai University1

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Sumber metadata: OAI-PMH (metadata jurnal) http://ijpeds.iaescore.com/index.php/IJPEDS/oai, pertama di-harvest 8 Nov 2026, terakhir terlihat 8 Nov 2026.
Metadata asli (oai_dc) 
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	<dc:title xml:lang="en-US">Analysis of Binary DC Source Reduced Switch 7-level Inverter</dc:title>
	<dc:creator>Arun, V.</dc:creator>
	<dc:creator>Shanthi, B.</dc:creator>
	<dc:creator>Arumugam, M.</dc:creator>
	<dc:description xml:lang="en-US">This paper proposes a binary DC source reduced switch 7-level inverter. Binary DC source reduced switch inverter is triggered by the Unipolar PWM strategy having sinusoidal and trapezoidal reference with triangular carriers. These Pulse Width Modulating (PWM) strategies include Phase Disposition (PD), Alternate Phase Opposition Disposition (APOD), Carrier Overlapping (CO). Performance factors like Total Harmonic Distortion (THD), VRMS (fundamental) and crest factor are evaluated for various modulation indices. Simulations were performed using MATLAB-SIMULINK. It is observed that UPDPWM strategy with trapezoidal reference provides output with relatively low distortion and UCOPWM strategy with trapezoidal reference provides relatively higher fundamental RMS output voltage.</dc:description>
	<dc:publisher xml:lang="en-US">Institute of Advanced Engineering and Science</dc:publisher>
	<dc:date>2015-03-01</dc:date>
	<dc:type>info:eu-repo/semantics/article</dc:type>
	<dc:type>info:eu-repo/semantics/publishedVersion</dc:type>
	<dc:type xml:lang="en-US"></dc:type>
	<dc:format>application/pdf</dc:format>
	<dc:identifier>https://ijpeds.iaescore.com/index.php/IJPEDS/article/view/5102</dc:identifier>
	<dc:identifier>10.11591/ijpeds.v6.i1.pp70-76</dc:identifier>
	<dc:source xml:lang="en-US">International Journal of Power Electronics and Drive Systems (IJPEDS); Vol 6, No 1: March 2015; 70-76</dc:source>
	<dc:source>2722-256X</dc:source>
	<dc:source>2088-8694</dc:source>
	<dc:source>10.11591/ijpeds.v6.i1</dc:source>
	<dc:language>eng</dc:language>
	<dc:relation>https://ijpeds.iaescore.com/index.php/IJPEDS/article/view/5102/4543</dc:relation>
	<dc:rights xml:lang="en-US">Copyright (c) 2015 V. Arun, B. Shanthi, M. Arumugam</dc:rights>
	<dc:rights xml:lang="en-US">http://creativecommons.org/licenses/by-sa/4.0</dc:rights>
</oai_dc:dc>