A proposed asymmetrical configuration of cascaded multilevel inverter topology for high level generation

Nanda, Lipika; Jena, Chitralekha; Pradhan, Arjyadhara; Panda, Babita

doi:10.11591/ijpeds.v13.i1.pp289-297

Akses terbuka Jurnal SINTA 1

A proposed asymmetrical configuration of cascaded multilevel inverter topology for high level generation

International Journal of Power Electronics and Drive Systems · Vol. 13 No. 1 (2022) · hlm. 289–297

DOI: 10.11591/ijpeds.v13.i1.pp289-297
ISSN: 2722-256X, 2088-8694
Terbit: 2022-03-01
Penerbit: Institute of Advanced Engineering and Science
Bahasa: eng
Lisensi: creativecommons.org/licenses/by-sa/4.0

Abstrak

Multilevel inverters are having high demand in high power applications. It works in medium voltage range. In this converter, for specific time intervals fewer switches will be conducting so switching loss is also reduced. This paper represents overall total harmonic distortion (THD) for different levels and different carrier frequencies. Switching loss, conduction loss of inverter has been discussed and hence inverter efficiency can be calculated. Phase displacement pulse width modulation method has been proposed in order to generate pulses. The proposed topology is well presented by its practical implementation with two current direct sources. All the simulations are being carried out using MATLAB/Simulink platform to validate the hardware results.

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20 penulis · 37 tautan kepenulisan bersama · 11 lintas organisasi

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KIIT University
ITM University
Vignan's Foundation for Science, Technology & Research
Poornima University
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Tampilkan sebagai tabel

Rekan penulis	Organisasi	Artikel bersama
Bhagabat Panda	KIIT University	3
Jayanta Kumar Sahu	Vignan's Foundation for Science, Technology & Research	2
Abhijit Dasgupta	KIIT University	2
Ullash Kumar Rout	KIIT University	2
K Chaitanya	Afiliasi tidak diketahui	2
Bhagbat Panda	Afiliasi tidak diketahui	1
Chinmoy Kumar Panigrahi	KIIT University	1
Sunita Pahadasingh	KIIT University	1
Sampurna Panda	ITM University	1
Rakesh Kumar	ITM University	1
Ashish Raj	Poornima University	1
K. Chitanya	Afiliasi tidak diketahui	1
Babita Panda	KIIT University	1
Sudhakar Sahu	KIIT University	1
Nivedita Pati	KIIT University	1
Jyoti Prasad Patra	Afiliasi tidak diketahui	1

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Sumber metadata: OAI-PMH (metadata jurnal) http://ijpeds.iaescore.com/index.php/IJPEDS/oai, pertama di-harvest 8 Nov 2026, terakhir terlihat 8 Nov 2026.

Metadata asli (oai_dc)

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	<dc:title xml:lang="en-US">A proposed asymmetrical configuration of cascaded multilevel inverter topology for high level generation</dc:title>
	<dc:creator>Nanda, Lipika</dc:creator>
	<dc:creator>Jena, Chitralekha</dc:creator>
	<dc:creator>Pradhan, Arjyadhara</dc:creator>
	<dc:creator>Panda, Babita</dc:creator>
	<dc:subject xml:lang="en-US">asymmetric MLI; bidirectional switch; switching loss; symmetric MLI; total harmonic distortion; voltage stress</dc:subject>
	<dc:description xml:lang="en-US">Multilevel inverters are having high demand in high power applications. It works in medium voltage range. In this converter, for specific time intervals fewer switches will be conducting so switching loss is also reduced. This paper represents overall total harmonic distortion (THD) for different levels and different carrier frequencies. Switching loss, conduction loss of inverter has been discussed and hence inverter efficiency can be calculated. Phase displacement pulse width modulation method has been proposed in order to generate pulses. The proposed topology is well presented by its practical implementation with two current direct sources. All the simulations are being carried out using MATLAB/Simulink platform to validate the hardware results.</dc:description>
	<dc:publisher xml:lang="en-US">Institute of Advanced Engineering and Science</dc:publisher>
	<dc:contributor xml:lang="en-US"></dc:contributor>
	<dc:date>2022-03-01</dc:date>
	<dc:type>info:eu-repo/semantics/article</dc:type>
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	<dc:identifier>https://ijpeds.iaescore.com/index.php/IJPEDS/article/view/21431</dc:identifier>
	<dc:identifier>10.11591/ijpeds.v13.i1.pp289-297</dc:identifier>
	<dc:source xml:lang="en-US">International Journal of Power Electronics and Drive Systems (IJPEDS); Vol 13, No 1: March 2022; 289-297</dc:source>
	<dc:source>2722-256X</dc:source>
	<dc:source>2088-8694</dc:source>
	<dc:source>10.11591/ijpeds.v13.i1</dc:source>
	<dc:language>eng</dc:language>
	<dc:relation>https://ijpeds.iaescore.com/index.php/IJPEDS/article/view/21431/13735</dc:relation>
	<dc:rights xml:lang="en-US">Copyright (c) 2022 Lipika Nanda, Chitralekha Jena, Arjyadhara Pradhan, Babita Panda</dc:rights>
	<dc:rights xml:lang="en-US">http://creativecommons.org/licenses/by-sa/4.0</dc:rights>
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