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An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification

Journal of ICT Research and Applications (JICTRA) · Vol. 3 No. 1 (2013) · pp. 51–66

DOI
10.5614/itbj.ict.2009.3.1.4
ISSN
2338-5499, 2337-5787
Published
2013-09-13
Publisher
DRI - ITB
Language
eng

Abstract

This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PC-based interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method.

Collaboration network of the authors

21 authors · 59 co-authorship links · 7 across different organisations

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Bandung Institute of Technology
  • Tokyo Institute of Technology
  • Andalas University
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Rachmad Vidya Wicaksana PutraBandung Institute of Technology6
Syifaul FuadaBandung Institute of Technology3
Nur AhmadiBandung Institute of Technology2
Maulana Yusuf FathanyBandung Institute of Technology2
Braham Lawas LawuBandung Institute of Technology2
Khilda AfifahBandung Institute of Technology2
Muhammad Husni SantriajiBandung Institute of Technology2
Rella MaretaBandung Institute of Technology1
Nurfitri AnbarsantiBandung Institute of Technology1
Rian FerdianAndalas University1
Febri DawaniBandung Institute of Technology1
Imran AbdurrahmanBandung Institute of Technology1
Angga Pratama PutraBandung Institute of Technology1
Yulian AskaBandung Institute of Technology1
Ahmad Zaky RamdaniBandung Institute of Technology1
Aditya Ferry ArdyantoBandung Institute of Technology1
Idham HafizhBandung Institute of Technology1
Septian Gilang Permana PutraBandung Institute of Technology1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

Metadata source: OAI-PMH (metadata jurnal) https://journals.itb.ac.id/index.php/jictra/oai, first harvested 26 Okt 2026, last seen 26 Okt 2026.
Original metadata (oai_dc)
<oai_dc:dc xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/  http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
	<dc:title xml:lang="en-US">An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification</dc:title>
	<dc:creator>Adiono, Trio</dc:creator>
	<dc:creator>Kerkhoff, Hans G.</dc:creator>
	<dc:creator>Kunieda, Hiroaki</dc:creator>
	<dc:description xml:lang="en-US">This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PC-based interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method.</dc:description>
	<dc:publisher xml:lang="en-US">DRI - ITB</dc:publisher>
	<dc:date>2013-09-13</dc:date>
	<dc:type>info:eu-repo/semantics/article</dc:type>
	<dc:type>info:eu-repo/semantics/publishedVersion</dc:type>
	<dc:type xml:lang="en-US">Peer-reviewed Article</dc:type>
	<dc:format>application/pdf</dc:format>
	<dc:identifier>https://journals.itb.ac.id/index.php/jictra/article/view/183</dc:identifier>
	<dc:identifier>10.5614/itbj.ict.2009.3.1.4</dc:identifier>
	<dc:source xml:lang="en-US">Journal of ICT Research and Applications; Vol. 3 No. 1 (2009); 51-66</dc:source>
	<dc:source>2338-5499</dc:source>
	<dc:source>2337-5787</dc:source>
	<dc:language>eng</dc:language>
	<dc:relation>https://journals.itb.ac.id/index.php/jictra/article/view/183/177</dc:relation>
</oai_dc:dc>