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A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm

Journal of ICT Research and Applications (JICTRA) · Vol. 6 No. 2 (2013) · pp. 131–150

DOI
10.5614/itbj.ict.2012.6.2.3
ISSN
2338-5499, 2337-5787
Published
2013-09-13
Publisher
DRI - ITB
Language
eng

Abstract

In the literature, several approaches of designing a DCT/IDCT-based image compression system have been proposed. In this paper, we present a new RTL design approach with as main focus developing a DCT/IDCT-based image compression architecture using a self-created algorithm. This algorithm can efficiently minimize the amount of shifter -adders to substitute multiplier s. We call this new algorithm the multiplication from Common Binary Expression (mCBE) Algorithm. Besides this algorithm, we propose alternative quantization numbers, which can be implemented simply as shifters in digital hardware. Mostly, these numbers can retain a good compressed-image quality compared to JPEG recommendations. These ideas lead to our design being small in circuit area, multiplierless, and low in complexity. The proposed 8-point 1D-DCT design has only six stages, while the 8-point 1D-IDCT design has only seven stages (one stage being defined as equal to the delay of one shifter or 2-input adder). By using the pipelining method, we can achieve a high-speed architecture with latency as a trade-off consideration. The design has been synthesized and can reach a speed of up to 1.41ns critical path delay (709.22MHz).

Collaboration network of the authors

21 authors · 59 co-authorship links · 7 across different organisations

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Bandung Institute of Technology
  • Tokyo Institute of Technology
  • Andalas University
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Syifaul FuadaBandung Institute of Technology5
Maulana Yusuf FathanyBandung Institute of Technology4
Braham Lawas LawuBandung Institute of Technology4
Khilda AfifahBandung Institute of Technology4
Muhammad Husni SantriajiBandung Institute of Technology4
Nur AhmadiBandung Institute of Technology3
Rian FerdianAndalas University2
Febri DawaniBandung Institute of Technology2
Imran AbdurrahmanBandung Institute of Technology2
Ahmad Zaky RamdaniBandung Institute of Technology2
Hans G. KerkhoffTokyo Institute of Technology1
Hiroaki KuniedaTokyo Institute of Technology1
Angga Pratama PutraBandung Institute of Technology1
Yulian AskaBandung Institute of Technology1
Aditya Ferry ArdyantoBandung Institute of Technology1
Idham HafizhBandung Institute of Technology1
Septian Gilang Permana PutraBandung Institute of Technology1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

Metadata source: OAI-PMH (metadata jurnal) https://journals.itb.ac.id/index.php/jictra/oai, first harvested 26 Okt 2026, last seen 26 Okt 2026.
Original metadata (oai_dc) 
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	<dc:title xml:lang="en-US">A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture  using the mCBE Algorithm</dc:title>
	<dc:creator>Putra, Rachmad Vidya Wicaksana</dc:creator>
	<dc:creator>Mareta, Rella</dc:creator>
	<dc:creator>Anbarsanti, Nurfitri</dc:creator>
	<dc:creator>Adiono, Trio</dc:creator>
	<dc:description xml:lang="en-US">In  the  literature, several approaches  of  designing  a  DCT/IDCT-based image compression system have been proposed.  In this paper,  we present a new RTL design approach with as main  focus developing a  DCT/IDCT-based image compression  architecture  using  a  self-created  algorithm.  This  algorithm  can efficiently  minimize  the  amount  of  shifter -adders  to  substitute  multiplier s.  We call  this  new  algorithm  the  multiplication  from  Common  Binary  Expression (mCBE)  Algorithm. Besides this algorithm, we propose alternative quantization numbers,  which  can  be  implemented  simply  as  shifters  in  digital  hardware. Mostly, these numbers can retain a good compressed-image quality  compared to JPEG  recommendations.  These  ideas  lead  to  our  design  being  small  in  circuit area,  multiplierless,  and  low  in  complexity.  The  proposed  8-point  1D-DCT design  has  only  six  stages,  while  the  8-point  1D-IDCT  design  has  only  seven stages  (one  stage  being  defined as  equal  to  the  delay  of  one  shifter  or  2-input adder). By using the pipelining method, we can achieve a high-speed architecture with latency as    a  trade-off consideration. The  design has been synthesized and can reach a speed of up to 1.41ns critical path delay (709.22MHz). </dc:description>
	<dc:publisher xml:lang="en-US">DRI - ITB</dc:publisher>
	<dc:date>2013-09-13</dc:date>
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	<dc:type xml:lang="en-US">Peer-reviewed Article</dc:type>
	<dc:format>application/pdf</dc:format>
	<dc:identifier>https://journals.itb.ac.id/index.php/jictra/article/view/225</dc:identifier>
	<dc:identifier>10.5614/itbj.ict.2012.6.2.3</dc:identifier>
	<dc:source xml:lang="en-US">Journal of ICT Research and Applications; Vol. 6 No. 2 (2012); 131-150</dc:source>
	<dc:source>2338-5499</dc:source>
	<dc:source>2337-5787</dc:source>
	<dc:language>eng</dc:language>
	<dc:relation>https://journals.itb.ac.id/index.php/jictra/article/view/225/219</dc:relation>
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