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An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA

Journal of ICT Research and Applications (JICTRA) · Vol. 12 No. 1 (2018) · pp. 70–86

DOI
10.5614/itbj.ict.res.appl.2018.12.1.5
ISSN
2338-5499, 2337-5787
Published
2018-04-30
Publisher
DRI - ITB
Language
eng

Abstract

Multiprocessor system-on-chip (MPSoC) promises better data management for parallel processing than conventional SoC. This feature is very suitable for wireless communication systems. Better data processing management can reduce resource utilization and can potentially reduce power consumption as well. Hence, this research aimed to minimize the orthogonal frequency-division multiple access (OFDMA) processing hardware by proposing a new data sharing architecture on a heterogeneous MPSoC platform that incorporates inter-processor communication (IPC), multi-processor, multi-bus, multi-frequency and parallel processing design of the medium access controller (MAC) layer. This MPSoC was designed based on a RISC processor with an AMBA multi-bus system. To achieve high throughput, the proposed MPSoC runs at two different frequencies, 40 MHz and 80 MHz. The proposed system was implemented and verified using FPGA. The verification results showed that the proposed system can work in real-time with a maximum throughput of 11 MBps using a 40 MHz system clock. The proposed MPSoC is a promising solution to perform OFDMA processing on 4G and 5G technologies.

Keywords

Collaboration network of the authors

25 authors · 69 co-authorship links · 7 across different organisations

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Bandung Institute of Technology
  • Tokyo Institute of Technology
  • Andalas University
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Syifaul FuadaBandung Institute of Technology5
Maulana Yusuf FathanyBandung Institute of Technology4
Braham Lawas LawuBandung Institute of Technology4
Khilda AfifahBandung Institute of Technology4
Muhammad Husni SantriajiBandung Institute of Technology4
Armein Z. R. LangiBandung Institute of Technology2
Amy Hamidah SalmanBandung Institute of Technology2
Richard MengkoAffiliation unknown2
Tati L. R. MengkoBandung Institute of Technology2
Rella MaretaBandung Institute of Technology2
Nurfitri AnbarsantiBandung Institute of Technology2
Ahmad Zaky RamdaniBandung Institute of Technology2
Aditya Ferry ArdyantoBandung Institute of Technology2
Idham HafizhBandung Institute of Technology2
Septian Gilang Permana PutraBandung Institute of Technology2
Hans G. KerkhoffTokyo Institute of Technology1
Hiroaki KuniedaTokyo Institute of Technology1
Angga Pratama PutraBandung Institute of Technology1
Yulian AskaBandung Institute of Technology1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

Metadata source: OAI-PMH (metadata jurnal) https://journals.itb.ac.id/index.php/jictra/oai, first harvested 26 Okt 2026, last seen 26 Okt 2026.
Original metadata (oai_dc) 
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	<dc:title xml:lang="en-US">An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA</dc:title>
	<dc:creator>Adiono, Trio</dc:creator>
	<dc:creator>Ferdian, Rian</dc:creator>
	<dc:creator>Dawani, Febri</dc:creator>
	<dc:creator>Abdurrahman, Imran</dc:creator>
	<dc:creator>Putra, Rachmad Vidya Wicaksana</dc:creator>
	<dc:creator>Ahmadi, Nur</dc:creator>
	<dc:subject xml:lang="en-US">IPC</dc:subject>
	<dc:subject xml:lang="en-US">MPSoC</dc:subject>
	<dc:subject xml:lang="en-US">multi-bus</dc:subject>
	<dc:subject xml:lang="en-US">multi-frequency</dc:subject>
	<dc:subject xml:lang="en-US">OFDMA.</dc:subject>
	<dc:description xml:lang="en-US">Multiprocessor system-on-chip (MPSoC) promises better data management for parallel processing than conventional SoC. This feature is very suitable for wireless communication systems. Better data processing management can reduce resource utilization and can potentially reduce power consumption as well. Hence, this research aimed to minimize the orthogonal frequency-division multiple access (OFDMA) processing hardware by proposing a new data sharing architecture on a heterogeneous MPSoC platform that incorporates inter-processor communication (IPC), multi-processor, multi-bus, multi-frequency and parallel processing design of the medium access controller (MAC) layer. This MPSoC was designed based on a RISC processor with an AMBA multi-bus system. To achieve high throughput, the proposed MPSoC runs at two different frequencies, 40 MHz and 80 MHz. The proposed system was implemented and verified using FPGA. The verification results showed that the proposed system can work in real-time with a maximum throughput of 11 MBps using a 40 MHz system clock. The proposed MPSoC is a promising solution to perform OFDMA processing on 4G and 5G technologies.</dc:description>
	<dc:publisher xml:lang="en-US">DRI - ITB</dc:publisher>
	<dc:date>2018-04-30</dc:date>
	<dc:type>info:eu-repo/semantics/article</dc:type>
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	<dc:type xml:lang="en-US">Peer-reviewed Article</dc:type>
	<dc:format>application/pdf</dc:format>
	<dc:identifier>https://journals.itb.ac.id/index.php/jictra/article/view/3512</dc:identifier>
	<dc:identifier>10.5614/itbj.ict.res.appl.2018.12.1.5</dc:identifier>
	<dc:source xml:lang="en-US">Journal of ICT Research and Applications; Vol. 12 No. 1 (2018); 70-86</dc:source>
	<dc:source>2338-5499</dc:source>
	<dc:source>2337-5787</dc:source>
	<dc:source>10.5614/itbj.ict.res.appl.2018.12.1</dc:source>
	<dc:language>eng</dc:language>
	<dc:relation>https://journals.itb.ac.id/index.php/jictra/article/view/3512/3254</dc:relation>
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