Melola Discovery

← Melola Discovery

Open access Jurnal SINTA 1

High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 6 No. 1 (2016)

DOI
10.11591/ijece.v6i1.8388
ISSN
2088-8708, 2088-8708
Published
2016-02-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc-nd/4.0

Abstract

The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.

Collaboration network of the authors

17 authors · 27 co-authorship links · 13 across different organisations

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Université Moulay Ismail de Meknes
  • Université Sultan Moulay Slimane
  • Mohammed V University
  • Université Ibn-Tofail
  • Abdelmalek Essaâdi University
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Zineb MekriniUniversité Moulay Ismail de Meknes3
Adil SaadiUniversité Moulay Ismail de Meknes2
Mohammed Amine IhedraneUniversité Moulay Ismail de Meknes1
El Fadl AdibaUniversité Ibn-Tofail1
Nejwa El MaammarUniversité Moulay Ismail de Meknes1
Jaouad FoshiUniversité Moulay Ismail de Meknes1
Asmae BabayaUniversité Moulay Ismail de Meknes1
Lahbib ZenkouarMohammed V University1
Mohammed LahsainiUniversité Moulay Ismail de Meknes1
Aziz El FatimiMohammed V University1
Youssef BaalaUniversité Moulay Ismail de Meknes1
Ibrahime Hassan NejdiUniversité Sultan Moulay Slimane1
Youssef RhaziUniversité Sultan Moulay Slimane1
Mustapha Ait LafkihUniversité Sultan Moulay Slimane1
Mohammed LamsalliAbdelmalek Essaâdi University1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys</dc:title><dc:creator>Oukili, Soufiane</dc:creator><dc:creator>Bri, Seddik</dc:creator><dc:description>&lt;jats:p&gt;&amp;lt;span lang="EN-US"&amp;gt;The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.&amp;lt;/span&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2016-02-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v6i1.8388</dc:identifier><dc:identifier>10.11591/ijece.v6i1.8388</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 6 No 1 (2016); 298</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://www.iaescore.com/journals/index.php/IJECE/article/viewFile/108/124</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc-nd/4.0</dc:rights></oai_dc:dc>