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FPGA Hardware Realization: Addition of Two Digital Signals Based on Walsh Transforms

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 6 No. 6 (2016)

DOI
10.11591/ijece.v6i6.12040
ISSN
2088-8708, 2088-8708
Published
2016-12-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc-nd/4.0

Abstract

This paper presents hardware realization of addition of two digital signals based on Walsh transforms and inverse Walsh transforms targeted to the Xilinx FPGA Spartan 3 board. The realization utilizes Walsh Transform to convert the input data to frequency domain and the inverse Walsh transform to reconvert the data from frequency domain. The designed system is capable of performing addition, subtraction, multiplication and Arbitrary Waveform Generation (AWG). However, in the present work, the hardware realization of addition only has been demonstrated. The Clock frequency for realization into the board is supplied by an external function generator. Output results are captured using a logic analyzer. Input data to the board (system) is passed manually through the available slide switches on-board.

Collaboration network of the authors

7 authors · 9 co-authorship links · 3 across different organisations

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  • Universitas Syiah Kuala
  • King Saud University
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Abdulrahman M. AlamoudKing Saud University2
Yuwaldi AwayUniversitas Syiah Kuala1
Rafiqa Shahnaz NoorUniversitas Syiah Kuala1
Hubbul WalidainyUniversitas Syiah Kuala1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>FPGA Hardware Realization: Addition of Two Digital Signals Based on Walsh Transforms</dc:title><dc:creator>Zulfikar, Zulfikar</dc:creator><dc:creator>Abbasi, Shuja A</dc:creator><dc:creator>Alamoud, Abdul Rahman M</dc:creator><dc:description>&lt;jats:p&gt;&amp;lt;p&amp;gt;This paper presents hardware realization of addition of two digital signals based on Walsh transforms and inverse Walsh transforms targeted to the Xilinx FPGA Spartan 3 board. The realization utilizes Walsh Transform to convert the input data to frequency domain and the inverse Walsh transform to reconvert the data from frequency domain. The designed system is capable of performing addition, subtraction, multiplication and Arbitrary Waveform Generation (AWG). However, in the present work, the hardware realization of addition only has been demonstrated. The Clock frequency for realization into the board is supplied by an external function generator. Output results are captured using a logic analyzer. Input data to the board (system) is passed manually through the available slide switches on-board.&amp;lt;/p&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2016-12-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v6i6.12040</dc:identifier><dc:identifier>10.11591/ijece.v6i6.12040</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 6 No 6 (2016); 2688</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://www.iaescore.com/journals/index.php/IJECE/article/viewFile/5880/5684</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc-nd/4.0</dc:rights></oai_dc:dc>