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Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 7 No. 4 (2017)

DOI
10.11591/ijece.v7i4.pp2192-2205
ISSN
2088-8708, 2088-8708
Published
2017-08-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.

Collaboration network of the authors

4 authors · 6 co-authorship links · 5 across different organisations

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  • University of Monastir
  • Tunis El Manar University
  • University of Carthage
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
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Co-authorOrganisationJoint articles

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Functional Verification of Large-integers Circuits using a Cosimulation-based Approach</dc:title><dc:creator>Alimi, Nejmeddine</dc:creator><dc:creator>Lahbib, Younes</dc:creator><dc:creator>Machhout, Mohsen</dc:creator><dc:creator>Tourki, Rached</dc:creator><dc:description>&lt;jats:p&gt;Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2017-08-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v7i4.pp2192-2205</dc:identifier><dc:identifier>10.11591/ijece.v7i4.pp2192-2205</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 7 No 4 (2017); 2192</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/7761/7246</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>