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A New Instrumentation Amplifier Architecture Based on Differential Difference Amplifier for Biological Signal Processing

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 7 No. 2 (2017)

DOI
10.11591/ijece.v7i2.pp759-766
ISSN
2088-8708, 2088-8708
Published
2017-04-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

In this paper, a new Instrumentation Amplifier (IA) architecture for biological signal pro-cessing is proposed. First stage of the proposed IA architecture consists of fully balance differential difference amplifier and three resistors. Its second stage was designed by using differential difference amplifier and two resistors. The second stage has smaller number of resistors than that of conventional one. The IA architectures are simulated and compared by using 1P 2M 0:6-m CMOS process. From HSPICE simulation result, lower common-mode voltage can be achieved by the proposed IA architecture. Average common-mode gain (Ac) of the proposed IA architecture is 31:26 dB lower than that of conventional one under 3% resistor mismatches condition. Therefore, the Ac of the proposed IA architecture is more insensitive to resistor mismatches and suitable for biological signal processing.

Collaboration network of the authors

11 authors · 23 co-authorship links · 7 across different organisations

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  • University of Miyazaki
  • University of Brawijaya
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
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Co-authorOrganisationJoint articles
Ryoichi MiyauchiUniversity of Miyazaki5
Agung SetiabudiAffiliation unknown4
Adharul MuttaqinUniversity of Brawijaya2
Kenya KondoUniversity of Miyazaki2
Stefanus Dion FinnadiUniversity of Brawijaya1
Kakeru ArakiUniversity of Miyazaki1
Nauval AryawiratamaUniversity of Brawijaya1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>A New Instrumentation Amplifier Architecture Based on Differential Difference Amplifier for Biological Signal Processing</dc:title><dc:creator>Abidin, Zainul</dc:creator><dc:creator>Tanno, Koichi</dc:creator><dc:creator>Mago, Shota</dc:creator><dc:creator>Tamura, Hiroki</dc:creator><dc:description>&lt;jats:p&gt;&amp;lt;p&amp;gt;In this paper, a new Instrumentation Amplifier (IA) architecture for biological signal pro-cessing is proposed. First stage of the proposed IA architecture consists of fully balance differential difference amplifier and three resistors. Its second stage was designed by using differential difference amplifier and two resistors. The second stage has smaller number of resistors than that of conventional one. The IA architectures are simulated and compared by using 1P 2M 0:6-m CMOS process. From HSPICE simulation result, lower common-mode voltage can be achieved by the proposed IA architecture. Average common-mode gain (Ac) of the proposed IA architecture is 31:26 dB lower than that of conventional one under 3% resistor mismatches condition. Therefore, the Ac of the proposed IA architecture is more insensitive to resistor mismatches and suitable for biological signal processing.&amp;lt;/p&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2017-04-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v7i2.pp759-766</dc:identifier><dc:identifier>10.11591/ijece.v7i2.pp759-766</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 7 No 2 (2017); 759</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/6422/6539</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>