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Performance Analysis of 3-Level 5-Phase Multilevel Inverter Topologies

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 7 No. 4 (2017)

DOI
10.11591/ijece.v7i4.pp1696-1705
ISSN
2088-8708, 2088-8708
Published
2017-08-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

Now a day’s many industrial applications requires high power. Some other appliances may require intermediate power either more or less depending upon their operation. With these consequences, MULTI LEVEL INVERTERS are introduced in 1975.for above intermediate voltage applications. The name MULTI LEVEL began with the three-level converter.By enormous advancement in power semiconductor switches, in electric drives increasing the phase number greater than the conventional three phase especially in locomotives, naval, aerospace, and electrical vehicles industry has many advantages than three phase. In this view, here five phase VSI has developed. This paper aims at comparing the performance of conventional two level inverter Diode clamped and Capacitor clamped topologies of 5-phase multilevel inverter (3-level) using sinusoidal pulse width modulation. SPWM is highly economical, has more efficiency, controllability. These circuits are analyzed by using simulation software package such as MATLAB.

Collaboration network of the authors

5 authors · 5 co-authorship links · 2 across different organisations

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Koneru Lakshmaiah Education Foundation
  • Prasad V. Potluri Siddhartha Institute of Technology
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
M.Venugopala RaoAffiliation unknown2
D. V. Ashok KumarAffiliation unknown1
B. Mabu SarifKoneru Lakshmaiah Education Foundation1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Performance Analysis of 3-Level 5-Phase Multilevel Inverter Topologies</dc:title><dc:creator>Jyothi, B.</dc:creator><dc:creator>Gopala Rao, M. Venu</dc:creator><dc:description>&lt;jats:p&gt;Now a day’s many industrial applications requires high power. Some other appliances may require intermediate power either more or less depending upon their operation. With these consequences, MULTI LEVEL INVERTERS are introduced in 1975.for above intermediate voltage applications. The name MULTI LEVEL began with the three-level converter.By enormous advancement in power semiconductor switches, in electric drives increasing the phase number greater than the conventional three phase especially in locomotives, naval, aerospace, and electrical vehicles industry has many advantages than three phase. In this view, here five phase VSI has developed. This paper aims at comparing the performance of conventional two level inverter Diode clamped and Capacitor clamped topologies of 5-phase multilevel inverter (3-level) using sinusoidal pulse width modulation. SPWM is highly economical, has more efficiency, controllability. These circuits are analyzed by using simulation software package such as MATLAB.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2017-08-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v7i4.pp1696-1705</dc:identifier><dc:identifier>10.11591/ijece.v7i4.pp1696-1705</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 7 No 4 (2017); 1696</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/7707/7193</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>