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Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with MATLAB/Simulink Implementation

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 8 No. 3 (2018)

DOI
10.11591/ijece.v8i3.pp1488-1497
ISSN
2088-8708, 2088-8708
Published
2018-06-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zero-voltage switching simulation results were satisfactory with 90% efficiency under full load condition.

Collaboration network of the authors

13 authors · 27 co-authorship links · 5 across different organisations

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  • Universiti Teknologi Petronas
  • University of Ilorin
  • National Agency for Science and Engineering Infrastructure
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Mohd A.F. RosliAffiliation unknown2
Zuhairi BaharudinAffiliation unknown2
Vijanth Sagayan AsirvadamUniversiti Teknologi Petronas1
Sabo Miya HassanUniversiti Teknologi Petronas1
Rosdiazli IbrahimUniversiti Teknologi Petronas1
Kishore BingiUniversiti Teknologi Petronas1
Tran Duc ChungUniversiti Teknologi Petronas1
S. A. Y. AmudaUniversity of Ilorin1
Olatunji Obalowu MohammedUniversity of Ilorin1
Ganiyu A. KareemNational Agency for Science and Engineering Infrastructure1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with MATLAB/Simulink Implementation</dc:title><dc:creator>Ibrahim, Oladimeji</dc:creator><dc:creator>Yahaya, Nor Zaihar</dc:creator><dc:creator>Saad, Nordin</dc:creator><dc:description>&lt;jats:p&gt;Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zero-voltage switching simulation results were satisfactory with 90% efficiency under full load condition.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2018-06-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v8i3.pp1488-1497</dc:identifier><dc:identifier>10.11591/ijece.v8i3.pp1488-1497</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 8 No 3 (2018); 1488</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/10069/8691</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>