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Design and implementation of secured agent based NoC using shortest path routing algorithm

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 9 No. 2 (2019)

DOI
10.11591/ijece.v9i2.pp950-959
ISSN
2088-8708, 2088-8708
Published
2019-04-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.

Collaboration network of the authors

7 authors · 13 co-authorship links

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • R.V. College of Engineering
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
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Co-authorOrganisationJoint articles
G. SrikanthR.V. College of Engineering1
S.R. YadhurajR.V. College of Engineering1
T.K. SubramanyamR.V. College of Engineering1
Satheesh Babu GandlaR.V. College of Engineering1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Design and implementation of secured agent based NoC using shortest path routing algorithm</dc:title><dc:creator>S, Kendaganna Swamy</dc:creator><dc:creator>Jatti, Anand</dc:creator><dc:creator>V., Uma B.</dc:creator><dc:description>&lt;jats:p&gt;Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2019-04-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v9i2.pp950-959</dc:identifier><dc:identifier>10.11591/ijece.v9i2.pp950-959</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 9 No 2 (2019); 950</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/12132/11596</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>