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Improve performance of the digital sinusoidal generator in FPGA by memory usage optimization

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 9 No. 3 (2019)

DOI
10.11591/ijece.v9i3.pp1742-1749
ISSN
2088-8708, 2088-8708
Published
2019-06-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

This paper presented the improvement in the performance of the digital sinusoidal signal generator, which was implemented in FPGA, by optimizing the usage of the available memory onboard. The sine wave was generated by using a Lookup Table method, where its pre-calculated values were stored in the onboard memory, and its frequency can be adjustable by changing the incremental step value of the memory address. In this proposed research, the memory stores only 25000 samples of the first quarter from a period of a sine wave and thus, the output signal accuracy was increased and the output frequency range was expanded, compared to the previous research. The proposed design was successfully developed and implemented in ALTERA Cyclone III DE0 FPGA Development Board, and its functionality was validated via functional simulation in Modelsim and also hardware experimental results observation in SignalTap II.

Collaboration network of the authors

33 authors · 94 co-authorship links · 15 across different organisations

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  • Universiti Teknikal Malaysia Melaka
  • Universiti Teknologi MARA
  • Universiti Malaysia Perlis
  • Universitas Ahmad Dahlan
  • University of Technology Malaysia
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Mohd Syafiq MispanUniversiti Teknikal Malaysia Melaka3
Siti Asma Che AzizUniversiti Teknikal Malaysia Melaka3
Ahmad Fauzan KadminUniversiti Teknikal Malaysia Melaka2
Norain RahimUniversiti Teknikal Malaysia Melaka2
Tole SutiknoUniversitas Ahmad Dahlan1
Auzani JidinUniversiti Teknikal Malaysia Melaka1
Nik Rumzi Nik IdrisUniversity of Technology Malaysia1
Lim Siau LiUniversiti Teknikal Malaysia Melaka1
Rostam Affendi HamzahUniversiti Teknikal Malaysia Melaka1
N. RahimUniversiti Teknikal Malaysia Melaka1
I. F. A. AzizUniversiti Teknikal Malaysia Melaka1
Mohd Saad HamidUniversiti Teknikal Malaysia Melaka1
D. Abd HadiUniversiti Teknikal Malaysia Melaka1
Norfariza Ab WahabUniversiti Teknikal Malaysia Melaka1
Z. MadihaUniversiti Teknikal Malaysia Melaka1
Nurliyana Abd MutalibUniversiti Teknikal Malaysia Melaka1
Siti Halma JohariUniversiti Teknikal Malaysia Melaka1
Suziana AhmadUniversiti Teknikal Malaysia Melaka1
M. NuzaimahUniversiti Teknikal Malaysia Melaka1
Ahmad Hafizzudin MustafaUniversiti Teknikal Malaysia Melaka1
Hafez SarkawiUniversiti Teknikal Malaysia Melaka1
Darmawaty Mohd AliUniversiti Teknologi MARA1
Murizah Binti KassimUniversiti Teknologi MARA1
Juwita Mohd SultanUniversiti Teknikal Malaysia Melaka1
Haslinah Mohd NasirUniversiti Teknikal Malaysia Melaka1
Muhammad Adni KamaruddinUniversiti Teknikal Malaysia Melaka1
N. I. M. NorUniversiti Malaysia Perlis1
Razaidi HussinUniversiti Malaysia Perlis1
Lee Weng FookAffiliation unknown1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Improve performance of the digital sinusoidal generator in FPGA by memory usage optimization</dc:title><dc:creator>Jidin, Aiman Zakwan</dc:creator><dc:creator>Mahzan, Irna Nadira</dc:creator><dc:creator>A. Subki, A. Shamsul Rahimi</dc:creator><dc:creator>Wan Hassan, Wan Haszerila</dc:creator><dc:description>&lt;jats:p&gt;&amp;lt;p&amp;gt;This paper presented the improvement in the performance of the digital sinusoidal signal generator, which was implemented in FPGA, by optimizing the usage of the available memory onboard. The sine wave was generated by using a Lookup Table method, where its pre-calculated values were stored in the onboard memory, and its frequency can be adjustable by changing the incremental step value of the memory address. In this proposed research, the memory stores only 25000 samples of the first quarter from a period of a sine wave and thus, the output signal accuracy was increased and the output frequency range was expanded, compared to the previous research. The proposed design was successfully developed and implemented in ALTERA Cyclone III DE0 FPGA Development Board, and its functionality was validated via functional simulation in Modelsim and also hardware experimental results observation in SignalTap II.&amp;lt;/p&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2019-06-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v9i3.pp1742-1749</dc:identifier><dc:identifier>10.11591/ijece.v9i3.pp1742-1749</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 9 No 3 (2019); 1742</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/17259/12346</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>