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Low Common-Mode Gain Instrumentation Amplifier Architecture Insensitive to Resistor Mismatches

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 6 No. 6 (2016)

DOI
10.11591/ijece.v6i6.pp3247-3254
ISSN
2088-8708, 2088-8708
Published
2016-12-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

In this paper, an instrumentation amplifier architecture for biological signal is proposed. First stage of conventional IA architecture was modified by using fully balanced differential difference amplifier and evaluated by using 1P 2M 0.6 μ m CMOS process. From HSPICE simulation result, lower common-mode voltage can be achieved by proposed IA architecture. Actual fabrication was done and six chips were evaluated. From the evaluation result, average common-mode gain of proposed IA architecture is 10.84 dB lower than that of conventional one without requiring well-matched resistors. Therefore, the proposed IA architecture is suitable for biological signal processing.

Collaboration network of the authors

11 authors · 23 co-authorship links · 7 across different organisations

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  • University of Miyazaki
  • University of Brawijaya
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Ryoichi MiyauchiUniversity of Miyazaki5
Agung SetiabudiAffiliation unknown4
Adharul MuttaqinUniversity of Brawijaya2
Kenya KondoUniversity of Miyazaki2
Stefanus Dion FinnadiUniversity of Brawijaya1
Kakeru ArakiUniversity of Miyazaki1
Nauval AryawiratamaUniversity of Brawijaya1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref 
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Low Common-Mode Gain Instrumentation Amplifier Architecture Insensitive to Resistor Mismatches</dc:title><dc:creator>Abidin, Zainul</dc:creator><dc:creator>Tanno, Koichi</dc:creator><dc:creator>Mago, Shota</dc:creator><dc:creator>Tamura, Hiroki</dc:creator><dc:description>&lt;jats:p&gt;&amp;lt;pre&amp;gt;In this paper, an instrumentation amplifier architecture for biological &amp;lt;br /&amp;gt;signal is proposed. First stage of conventional IA architecture was modified &amp;lt;br /&amp;gt;by using fully balanced differential difference amplifier and evaluated by &amp;lt;br /&amp;gt;using &amp;lt;span&amp;gt;1P&amp;lt;/span&amp;gt; &amp;lt;span&amp;gt;2M&amp;lt;/span&amp;gt; 0.6&amp;lt;span&amp;gt;μ&amp;lt;/span&amp;gt;m CMOS process. From &amp;lt;span&amp;gt;HSPICE&amp;lt;/span&amp;gt; simulation result, lower &amp;lt;br /&amp;gt;common-mode voltage can be achieved by proposed IA architecture. &amp;lt;br /&amp;gt;Actual fabrication was done and six chips were evaluated. From the evaluation result, average common-mode gain of proposed IA architecture &amp;lt;br /&amp;gt;is &amp;lt;span&amp;gt;10.84&amp;lt;/span&amp;gt; dB lower than that of conventional one without requiring &amp;lt;br /&amp;gt;well-matched resistors. Therefore, the proposed IA architecture &amp;lt;br /&amp;gt;is suitable for biological signal processing.&amp;lt;br /&amp;gt;&amp;lt;br /&amp;gt;&amp;lt;/pre&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2016-12-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v6i6.pp3247-3254</dc:identifier><dc:identifier>10.11591/ijece.v6i6.pp3247-3254</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 6 No 6 (2016); 3247</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/5946/5711</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>