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Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA
International Journal of Electrical and Computer Engineering (IJECE) · Vol. 6 No. 2 (2016)
ISSN 2088-8708, 2088-8708
Published 2016-04-01
Publisher Institute of Advanced Engineering and Science
Abstract
In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.
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Koneru Lakshmaiah Education Foundation Affiliation unknown
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Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works,
first harvested 27 Okt 2026,
last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA</dc:title><dc:creator>Babu T, Narendra</dc:creator><dc:creator>Noorbasha, Fazal</dc:creator><dc:creator>Chowdary Gunnam, Leenendra</dc:creator><dc:description><jats:p>In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.</jats:p></dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2016-04-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v6i2.pp602-610</dc:identifier><dc:identifier>10.11591/ijece.v6i2.pp602-610</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 6 No 2 (2016); 602</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/140/156</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>
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Cite this article
APA 7
Babu T, N., Noorbasha, F., & Chowdary Gunnam, L. (2016). Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA. International Journal of Electrical and Computer Engineering (IJECE), 6(2). https://doi.org/10.11591/ijece.v6i2.pp602-610
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IEEE
N. Babu T, F. Noorbasha, and L. Chowdary Gunnam, “Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA,” International Journal of Electrical and Computer Engineering (IJECE), vol. 6, no. 2, 2016, doi: 10.11591/ijece.v6i2.pp602-610.
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