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Study of Data Security Algorithms using Verilog HDL

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 5 No. 5 (2015)

DOI
10.11591/ijece.v5i5.pp1092-1101
ISSN
2088-8708, 2088-8708
Published
2015-10-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.

Collaboration network of the authors

6 authors · 9 co-authorship links

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  • Sathyabama Institute of Science and Technology
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
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Co-authorOrganisationJoint articles
N. R. KrishnamoorthySathyabama Institute of Science and Technology1
Jerry AlexanderSathyabama Institute of Science and Technology1
D. MarshianaSathyabama Institute of Science and Technology1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref 
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Study of Data Security Algorithms using Verilog HDL</dc:title><dc:creator>Sumathi, M.</dc:creator><dc:creator>Nirmala, D.</dc:creator><dc:creator>Rajkumar, R. Immanuel</dc:creator><dc:description>&lt;jats:p&gt;This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2015-10-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v5i5.pp1092-1101</dc:identifier><dc:identifier>10.11591/ijece.v5i5.pp1092-1101</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 5 No 5 (2015); 1092</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/5730/4607</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>