An Improved Design of Linear Congruential Generator based on Wordlengths Reduction Technique into FPGA

Abstract

This paper exposes an improved design of linear congruential generator (LCG) based on wordlengths reduction technique into FPGA. The circuit is derived from LCG algorithm proposed by Lehmer and the previous design. The wordlengths reduction technique has been developed more in order to simplify further circuit. The proposed design based on the fact that in applications only specific input data were used. Some nets connections between blocks of the circuit are ignored or truncated. Simulations either behavior or timing have been done and the results is similar to its algorithm. Four best Xilinx chips have been chosen to extract comparison data of speed and occupied area. Further comparison of occupied area in terms of flip-flop and full adder has been made. In general, the proposed design overcome the previous published LCG circuit.