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Accurate leakage current models for MOSFET nanoscale devices

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 10 No. 3 (2020)

DOI
10.11591/ijece.v10i3.pp2313-2321
ISSN
2088-8708, 2088-8708
Published
2020-06-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (

Collaboration network of the authors

3 authors · 3 co-authorship links

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  • Jordan University of Science and Technology
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Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref 
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Accurate leakage current models for MOSFET nanoscale devices</dc:title><dc:creator>Rjoub, Abdoul</dc:creator><dc:creator>Mistarihi, Mamoun</dc:creator><dc:creator>Taradeh, Nedal Al</dc:creator><dc:description>&lt;jats:p&gt;This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (&amp;lt;5nm) have been investigated. Simulation results using HSPICEexhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2020-06-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v10i3.pp2313-2321</dc:identifier><dc:identifier>10.11591/ijece.v10i3.pp2313-2321</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 10 No 3 (2020); 2313</dc:source><dc:source>2088-8708</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/20337/pdf</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>