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An efficient hardware logarithm generator with modified quasi-symmetrical approach for digital signal processing

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 10 No. 5 (2020)

DOI
10.11591/ijece.v10i5.pp4671-4678
ISSN
2722-2578, 2088-8708
Published
2020-10-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-nc/4.0

Abstract

This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.

Collaboration network of the authors

5 authors · 10 co-authorship links

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  • Le Quy Don Technical University
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
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Co-authorOrganisationJoint articles
Van‐Phuc HoangLe Quy Don Technical University1
Thanh QuanLe Quy Don Technical University1
Dinh-Nhan LeLe Quy Don Technical University1
Duong Du BuiAffiliation unknown1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref 
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>An efficient hardware logarithm generator with modified quasi-symmetrical approach for digital signal processing</dc:title><dc:creator>Nguyen, Minh-Hong</dc:creator><dc:description>&lt;jats:p&gt;This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2020-10-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v10i5.pp4671-4678</dc:identifier><dc:identifier>10.11591/ijece.v10i5.pp4671-4678</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 10 No 5 (2020); 4671</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/21229/14177</dc:relation><dc:rights>http://creativecommons.org/licenses/by-nc/4.0</dc:rights></oai_dc:dc>