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New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 12 No. 2 (2022)

DOI
10.11591/ijece.v12i2.pp1955-1964
ISSN
2722-2578, 2088-8708
Published
2022-04-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

This study aims to design a new architecture of the artificial neural networks (ANNs) using the Xilinx system generator (XSG) and its hardware co-simulation equivalent model using field programmable gate array (FPGA) to predict the behavior of Chua’s chaotic system and use it in hiding information. The work proposed consists of two main sections. In the first section, MATLAB R2016a was used to build a 3×4×3 feed forward neural network (FFNN). The training results demonstrate that FFNN training in the Bayesian regulation algorithm is sufficiently accurate to directly implement. The second section demonstrates the hardware implementation of the network with the XSG on the Xilinx artix7 xc7a100t-1csg324 chip. Finally, the message was first encrypted using a dynamic Chua system and then decrypted using ANN’s chaotic dynamics. ANN models were developed to implement hardware in the FPGA system using the IEEE 754 Single precision floating-point format. The ANN design method illustrated can be extended to other chaotic systems in general.

Collaboration network of the authors

3 authors · 3 co-authorship links

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  • University of Basrah
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  • Same organisation
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Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation</dc:title><dc:creator>Al-Musawi, Wisal Adnan</dc:creator><dc:creator>A. Wali, Wasan</dc:creator><dc:creator>Abd Ali Al-Ibadi, Mohammed</dc:creator><dc:description>&lt;jats:p&gt;&amp;lt;p&amp;gt;This study aims to design a new architecture of the artificial neural networks (ANNs) using the Xilinx system generator (XSG) and its hardware co-simulation equivalent model using field programmable gate array (FPGA) to predict the behavior of Chua’s chaotic system and use it in hiding information. The work proposed consists of two main sections. In the first section, MATLAB R2016a was used to build a 3×4×3 feed forward neural network (FFNN). The training results demonstrate that FFNN training in the Bayesian regulation algorithm is sufficiently accurate to directly implement. The second section demonstrates the hardware implementation of the network with the XSG on the Xilinx artix7 xc7a100t-1csg324 chip. Finally, the message was first encrypted using a dynamic Chua system and then decrypted using ANN’s chaotic dynamics. ANN models were developed to implement hardware in the FPGA system using the IEEE 754 Single precision floating-point format. The ANN design method illustrated can be extended to other chaotic systems in general.&amp;lt;/p&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2022-04-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v12i2.pp1955-1964</dc:identifier><dc:identifier>10.11591/ijece.v12i2.pp1955-1964</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 12 No 2 (2022); 1955</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/25418/15583</dc:relation><dc:rights>http://creativecommons.org/licenses/by-sa/4.0</dc:rights></oai_dc:dc>