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Open-circuit fault resilient ability multi level inverter with reduced switch count for off grid applications

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 12 No. 3 (2022)

DOI
10.11591/ijece.v12i3.pp2353-2362
ISSN
2722-2578, 2088-8708
Published
2022-06-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

In a multi-level inverter (MLI), the switching component number effect on volume and reliability is a major concern in on-grid and off-grid applications. The recent trend in MLI, reduced component number of power switches, and capacitors in multi-level inverter topologies have been driven for power conversion. The concept of fault tolerance is not considered in many such configurations; due to this the reliability of the MLI is very low. So now it is a major research concern, to develop a strong fault resilient ability power electronic converter. In this work, a novel configuration of a multilevel inverter with a lower switch count is proposed and analyzed with fault tolerance operation for improvement of reliability. Generally, the fault-tolerant operation is analyzed in only any one of the switches in MLI. But the proposed topology is concerned with multiple switch fault tolerance. Further, the phase disposition pulse width modulation (PDPWM) control scheme is utilized for the operation of the proposed inverter topology. The proposed inverter topology is simulated in MATLAB/Simulink environment under normal and faulty condition; the results are obtained and validated.

Collaboration network of the authors

5 authors · 6 co-authorship links · 4 across different organisations

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  • Lovely Professional University
  • Kakatiya University
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
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Co-authorOrganisationJoint articles
Narasimha Rao MucherlaLovely Professional University1
Madhukar Rao AKakatiya University1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Open-circuit fault resilient ability multi level inverter with reduced switch count for off grid applications</dc:title><dc:creator>Kumar Chillappagari, Pavan</dc:creator><dc:creator>Nagaraj, Karthick</dc:creator><dc:creator>Rao Airineni, Madhukar</dc:creator><dc:description>&lt;jats:p&gt;&amp;lt;p&amp;gt;In a multi-level inverter (MLI), the switching component number effect on volume and reliability is a major concern in on-grid and off-grid applications. The recent trend in MLI, reduced component number of power switches, and capacitors in multi-level inverter topologies have been driven for power conversion. The concept of fault tolerance is not considered in many such configurations; due to this the reliability of the MLI is very low. So now it is a major research concern, to develop a strong fault resilient ability power electronic converter. In this work, a novel configuration of a multilevel inverter with a lower switch count is proposed and analyzed with fault tolerance operation for improvement of reliability. Generally, the fault-tolerant operation is analyzed in only any one of the switches in MLI. But the proposed topology is concerned with multiple switch fault tolerance. Further, the phase disposition pulse width modulation (PDPWM) control scheme is utilized for the operation of the proposed inverter topology. The proposed inverter topology is simulated in MATLAB/Simulink environment under normal and faulty condition; the results are obtained and validated.&amp;lt;/p&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2022-06-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v12i3.pp2353-2362</dc:identifier><dc:identifier>10.11591/ijece.v12i3.pp2353-2362</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 12 No 3 (2022); 2353</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/25998/15613</dc:relation><dc:rights>http://creativecommons.org/licenses/by-sa/4.0</dc:rights></oai_dc:dc>