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Capacitor current analysis of a three-level neutral point clamped converter under unbalanced loading conditions

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 13 No. 6 (2023)

DOI
10.11591/ijece.v13i6.pp6156-6173
ISSN
2722-2578, 2088-8708
Published
2023-12-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

A neutral point clamped (NPC) converter is considered a forefront in industrial applications. Supplying a typically balanced stand-alone load is one of those applications. However, the loading may become unbalanced which can impact the capacitors’ current and voltage ripple. In this work, an approach is proposed that analyze the capacitor current under unbalanced loading. The proposed method is based on a combination of two-dimensional Fourier series and symmetrical components. Since, two-dimensional Fourier series sectorize the spectrum into harmonics that are either defined by multiples of, fundamental, carrier or both frequencies, the method derives the Fourier coefficients for each sector, corresponding to a sequence current. Therefore, based on the presented approach, each harmonic amplitude in the spectrum sector is defined by three Fourier coefficients reflecting zero, positive and negative sequence current. The capacitor current spectrum is obtained by vector summing sequence coefficients. The method is tested on unbalanced load conditions with (out) a ground path. Results verify feasibility of the proposed method in deriving Fourier coefficients of capacitor currents that accurately reflects the loading status of the NPC. This is vital for converter design in terms of proper sizing of DC capacitor and can help in avoiding components failure.

Collaboration network of the authors

3 authors · 3 co-authorship links

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This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Capacitor current analysis of a three-level neutral point clamped converter under unbalanced loading conditions</dc:title><dc:creator>Thahab, Riyadh Toman</dc:creator><dc:creator>Al-Mhana, Tahani Hamodi</dc:creator><dc:creator>Thahab, Ahmed Toman</dc:creator><dc:description>&lt;jats:p&gt;A neutral point clamped (NPC) converter is considered a forefront in industrial applications. Supplying a typically balanced stand-alone load is one of those applications. However, the loading may become unbalanced which can impact the capacitors’ current and voltage ripple. In this work, an approach is proposed that analyze the capacitor current under unbalanced loading. The proposed method is based on a combination of two-dimensional Fourier series and symmetrical components. Since, two-dimensional Fourier series sectorize the spectrum into harmonics that are either defined by multiples of, fundamental, carrier or both frequencies, the method derives the Fourier coefficients for each sector, corresponding to a sequence current. Therefore, based on the presented approach, each harmonic amplitude in the spectrum sector is defined by three Fourier coefficients reflecting zero, positive and negative sequence current. The capacitor current spectrum is obtained by vector summing sequence coefficients. The method is tested on unbalanced load conditions with (out) a ground path. Results verify feasibility of the proposed method in deriving Fourier coefficients of capacitor currents that accurately reflects the loading status of the NPC. This is vital for converter design in terms of proper sizing of DC capacitor and can help in avoiding components failure.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2023-12-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v13i6.pp6156-6173</dc:identifier><dc:identifier>10.11591/ijece.v13i6.pp6156-6173</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 13 No 6 (2023); 6156</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>https://ijece.iaescore.com/index.php/IJECE/article/viewFile/27652/16942</dc:relation><dc:rights>http://creativecommons.org/licenses/by-sa/4.0</dc:rights></oai_dc:dc>