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Single-phase binary phase-shift keying, quadrature phase shift keying demodulators using an XOR gate as a phase detector

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 13 No. 6 (2023)

DOI
10.11591/ijece.v13i6.pp6092-6101
ISSN
2722-2578, 2088-8708
Published
2023-12-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

A single-phase/single-loop multiple-phase-shift-keying ( m -PSK) demodulator is described. The demodulator relies on a linear range of an exclusive-OR (XOR) gate employed as a phase detector. The phase controller takes the average output from the XOR gate and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for an m -PSK signal. The proposed single-phase binary-/quadrature-PSK (BPSK/QPSK) demodulators have been implemented with low-cost discrete components. The core of the phase controller simply relies on number of stages of a full-wave rectifier and a linear amplifier built from well-known op-amp-based negative feedback circuits. The demodulator prototypes operate from a single supply of 5 V. At a carrier frequency of 100 kHz, both the BPSK and QPSK demodulators achieved the maximum symbol rate of 20 ksymbol/s respectively. At these symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 2×10 -10 and 7×10 -10.

Collaboration network of the authors

4 authors · 3 co-authorship links

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  • Prince of Songkla University
  • Different organisations
  • Same organisation
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Co-authorOrganisationJoint articles
Thannatorn BoonrungruedeePrince of Songkla University1
Chutpipat ChaichomnanPrince of Songkla University1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Single-phase binary phase-shift keying, quadrature phase shift keying demodulators using an XOR gate as a phase detector</dc:title><dc:creator>Kaewmunee, Apinut</dc:creator><dc:creator>Khumsat, Phanumas</dc:creator><dc:description>&lt;jats:p&gt;A single-phase/single-loop multiple-phase-shift-keying (&amp;lt;em&amp;gt;&amp;lt;span lang="EN-US"&amp;gt;m&amp;lt;/span&amp;gt;&amp;lt;/em&amp;gt;&amp;lt;span lang="EN-US"&amp;gt;-PSK)&amp;lt;/span&amp;gt;&amp;lt;span lang="EN-US"&amp;gt; demodulator is described. The demodulator relies on a linear range of an exclusive-OR (XOR) gate employed as a phase detector. The phase controller takes the average output from the XOR gate and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for an &amp;lt;/span&amp;gt;&amp;lt;em&amp;gt;&amp;lt;span lang="EN-US"&amp;gt;m&amp;lt;/span&amp;gt;&amp;lt;/em&amp;gt;&amp;lt;span lang="EN-US"&amp;gt;-PSK signal. The proposed single-phase binary-/quadrature-PSK (BPSK/QPSK) demodulators have been implemented with low-cost discrete components. The core of the phase controller simply relies on number of stages of a full-wave rectifier and a linear amplifier built from well-known op-amp-based negative feedback circuits. The demodulator prototypes operate from a single supply of 5 V. At a carrier frequency of 100 kHz, both the BPSK and QPSK demodulators achieved the maximum symbol rate of 20 ksymbol/s respectively. At these symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 2×10&amp;lt;sup&amp;gt;-10 &amp;lt;/sup&amp;gt;and 7×10&amp;lt;sup&amp;gt;-10&amp;lt;/sup&amp;gt;.&amp;lt;/span&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2023-12-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v13i6.pp6092-6101</dc:identifier><dc:identifier>10.11591/ijece.v13i6.pp6092-6101</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 13 No 6 (2023); 6092</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>https://ijece.iaescore.com/index.php/IJECE/article/viewFile/30922/16937</dc:relation><dc:rights>http://creativecommons.org/licenses/by-sa/4.0</dc:rights></oai_dc:dc>