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An efficient adaptive reconfigurable routing protocol for optimized data packet distribution in network on chips

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 14 No. 1 (2024)

DOI
10.11591/ijece.v14i1.pp305-314
ISSN
2722-2578, 2088-8708
Published
2024-02-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

The deadlock-free and live lock-free routing at the same time is minimized in the network on chip (NoC) using the proposed adoptive reconfigurable routing protocol (ARRP). Congestion condition emergencies are avoided using the proposed algorithm. The input packet distribution process is improved among all its shortest paths of output points. The performance analysis has been initiated by considering different configuration (N*N) mesh networks, by sending various ranges of data packets to the network on chip. The average and maximum power dissipation of XY, odd-even, Dy-XY algorithm, and proposed algorithm are determined. In this paper, an analysis of gate utilization during data packet transfer in various mesh configurations is carried out. The number of cycles required for each message injection in different mesh configurations is analyzed. The proposed routing algorithm is implemented and compared with conventional algorithms. The simulation has been carried out using reconfigurable two-dimensional mesh for the NoC. The proposed algorithm has been implemented considering array size, the routing operating frequency, link width length, value of probability, and traffic types. The proposed ARRP algorithm reduces the average latency, avoids routing congestion, and is more feasible for NoC compared to conventional methods.

Collaboration network of the authors

18 authors · 41 co-authorship links · 13 across different organisations

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Don Bosco Institute of Technology
  • Visvesvaraya Technological University
  • Christ University
  • Kammavari Sangham Institute of Technology
  • Indian Academy of Sciences
  • REVA University
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
K. R. RekhaVisvesvaraya Technological University3
Nataraj Kanathur RamaswamyDon Bosco Institute of Technology3
Rathod ShivajiVisvesvaraya Technological University1
Divyashree Yamadur VenkateshAffiliation unknown1
Komala MallikarjunaiahAffiliation unknown1
Sadiya ThazeenAffiliation unknown1
Chandana ChikkasiddaiahAffiliation unknown1
Govindaswamy ParthasarathyREVA University1
Mamatha M. PandithDon Bosco Institute of Technology1
Anitha Narasimha MurthyAffiliation unknown1
Rekha SathyanarayanaDon Bosco Institute of Technology1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>An efficient adaptive reconfigurable routing protocol for optimized data packet distribution in network on chips</dc:title><dc:creator>Goravi Sukumar, Pavithra</dc:creator><dc:creator>Krishnaiah, Modugu</dc:creator><dc:creator>Velluri, Rekha</dc:creator><dc:creator>Satish, Pooja</dc:creator><dc:creator>Nagaraju, Sharmila</dc:creator><dc:creator>Gowda Puttaswamy, Nandini</dc:creator><dc:creator>Srikantaswamy, Mallikarjunaswamy</dc:creator><dc:description>&lt;jats:p&gt;The deadlock-free and live lock-free routing at the same time is minimized in the network on chip (NoC) using the proposed adoptive reconfigurable routing protocol (ARRP). Congestion condition emergencies are avoided using the proposed algorithm. The input packet distribution process is improved among all its shortest paths of output points. The performance analysis has been initiated by considering different configuration (N*N) mesh networks, by sending various ranges of data packets to the network on chip. The average and maximum power dissipation of XY, odd-even, Dy-XY algorithm, and proposed algorithm are determined. In this paper, an analysis of gate utilization during data packet transfer in various mesh configurations is carried out. The number of cycles required for each message injection in different mesh configurations is analyzed. The proposed routing algorithm is implemented and compared with conventional algorithms. The simulation has been carried out using reconfigurable two-dimensional mesh for the NoC. The proposed algorithm has been implemented considering array size, the routing operating frequency, link width length, value of probability, and traffic types. The proposed ARRP algorithm reduces the average latency, avoids routing congestion, and is more feasible for NoC compared to conventional methods.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2024-02-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v14i1.pp305-314</dc:identifier><dc:identifier>10.11591/ijece.v14i1.pp305-314</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 14 No 1 (2024); 305</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>https://ijece.iaescore.com/index.php/IJECE/article/viewFile/32309/17082</dc:relation><dc:rights>http://creativecommons.org/licenses/by-sa/4.0</dc:rights></oai_dc:dc>