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Hardware-in-the-loop setup for enhanced modular multi-level converter with reduced circulating currents

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 14 No. 2 (2024)

DOI
10.11591/ijece.v14i2.pp1448-1458
ISSN
2722-2578, 2088-8708
Published
2024-04-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

Owing to its essential features, such as modularity and exceptional power quality, the modular multilevel converter (MMC) emerges as the optimal converter topology for high-voltage direct current (HVDC) applications. Traditionally, MMCs are controlled through a method called nearest level modulation (NLM), which generates N+1 AC output voltages, where N represents the number of sub modules (SMs) per arm. In this paper, we introduce a modified NLM technique designed to yield 2N+1 and 4N+1 levels, with a focus on efficiently controlling internal dynamics. The proposed MMC is evaluated using a hardware-in-the-loop (HIL) environment to obtain real-time simulation outcomes. This MMC topology demonstrates a reduction in circulating currents and capacitor voltage ripple.

Collaboration network of the authors

7 authors · 13 co-authorship links · 5 across different organisations

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Sukkur IBA University
  • Quaid-e-Awam University of Engineering, Science and Technology
  • Benazir Bhutto Shaheed University Lyari
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Safdar Ali AbroBenazir Bhutto Shaheed University Lyari1
Lyu Guang HuaAffiliation unknown1
J.A. LaghariQuaid-e-Awam University of Engineering, Science and Technology1
Muhammad Akram BhayoQuaid-e-Awam University of Engineering, Science and Technology1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>Hardware-in-the-loop setup for enhanced modular multi-level converter with reduced circulating currents</dc:title><dc:creator>Soomro, Jahangeer Badar</dc:creator><dc:creator>Ali, Khawaja Haider</dc:creator><dc:creator>Memon, Abdul Aziz</dc:creator><dc:description>&lt;jats:p&gt;Owing to its essential features, such as modularity and exceptional power quality, the modular multilevel converter (MMC) emerges as the optimal converter topology for high-voltage direct current (HVDC) applications. Traditionally, MMCs are controlled through a method called nearest level modulation (NLM), which generates N+1 AC output voltages, where N represents the number of sub modules (SMs) per arm. In this paper, we introduce a modified NLM technique designed to yield 2N+1 and 4N+1 levels, with a focus on efficiently controlling internal dynamics. The proposed MMC is evaluated using a hardware-in-the-loop (HIL) environment to obtain real-time simulation outcomes. This MMC topology demonstrates a reduction in circulating currents and capacitor voltage ripple.&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2024-04-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v14i2.pp1448-1458</dc:identifier><dc:identifier>10.11591/ijece.v14i2.pp1448-1458</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 14 No 2 (2024); 1448</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>https://ijece.iaescore.com/index.php/IJECE/article/viewFile/34346/17278</dc:relation><dc:rights>http://creativecommons.org/licenses/by-sa/4.0</dc:rights></oai_dc:dc>