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A new multilevel DC-AC converter topology with reduced switch using multicarrier sinusoidal pulse width modulation

International Journal of Power Electronics and Drive Systems · Vol. 11 No. 2 (2020) · pp. 752–761

DOI
10.11591/ijpeds.v11.i2.pp752-761
ISSN
2722-256X, 2088-8694
Published
2020-06-01
Publisher
Institute of Advanced Engineering and Science
Language
eng
License
creativecommons.org/licenses/by-sa/4.0

Abstract

Multilevel converters have a significant role in power processing control in the power system, which has some inherent features like reduced harmonics, high power & medium voltage, reduced voltage stress. In this proposed paper, a novel multilevel inverter with reduced number of switches and without passive components. The proposed inverter generates 15 level output voltage with suitable switching pulse generation using multicarrier sinusoidal pulse width modulation (MSPWM) and different level of voltages are obtained with variation of modulation index. Also coupled inductor is used to minimize the harmonic content and smoothing output current. The scheme which includes different range of unequal voltage sources. As a result, the proposed system it reduces switching control complexity and there is no voltage balancing problem. This paper elucidates the operating modes, voltage stress minimisation and harmonic reduction are discussed. The results of the proposed multilevel dc-ac converter are verified using matlab/simulink. The simulation & hardware results of the proposed inverter were verified using matlab simulink and dsPIC controller respectively, which was analysed with different voltage level and different modulation index.

Collaboration network of the authors

40 authors · 141 co-authorship links · 14 across different organisations · showing the 40 most connected

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • SRM Institute of Science and Technology
  • SRM University
  • American International University-Bangladesh
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Krishnasamy VijayakumarSRM Institute of Science and Technology13
S. George FernandezSRM Institute of Science and Technology8
A. VeluAffiliation unknown5
V. KalyanasundhramSRM Institute of Science and Technology5
K. SaravananSRM Institute of Science and Technology3
D. SattianadanSRM Institute of Science and Technology3
R. SridharSRM Institute of Science and Technology3
P. SureshAffiliation unknown3
Vaidheeswaran ArchanaAffiliation unknown3
Soham ChatterjeeAffiliation unknown3
V. SinmayeeAffiliation unknown3
Priyanka DasSRM Institute of Science and Technology2
Gaurav Kumar SinghSRM Institute of Science and Technology2
Sourav SinhaAmerican International University-Bangladesh2
Arnab NagSRM Institute of Science and Technology2
Arul Rayappan StalinSRM University2
P. GopiSRM University2
P. PonselvinSRM University2
C. S. BoopathiSRM Institute of Science and Technology2
A.U MutawakkilAffiliation unknown2
V. P. ArumbuAffiliation unknown2
P. DivyaAffiliation unknown2
K. Mani RahulanAffiliation unknown2
V. VenkatachalamSRM Institute of Science and Technology1
R. Mano NarayananSRM Institute of Science and Technology1
D. SaravanakumarSRM Institute of Science and Technology1
Th. Ankit SinghSRM Institute of Science and Technology1
Anamika RanjanSRM Institute of Science and Technology1
Jatin P SinghSRM Institute of Science and Technology1
Rohit SahasrabuddheSRM Institute of Science and Technology1
Mathur Kartik HiteshkumarSRM Institute of Science and Technology1
Jay Anil PuranikSRM Institute of Science and Technology1
N. SeethalakshmiAffiliation unknown1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

Metadata source: OAI-PMH (metadata jurnal) http://ijpeds.iaescore.com/index.php/IJPEDS/oai, first harvested 8 Nov 2026, last seen 8 Nov 2026.
Original metadata (oai_dc)
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	<dc:title xml:lang="en-US">A new multilevel DC-AC converter topology with reduced switch using multicarrier sinusoidal pulse width modulation</dc:title>
	<dc:creator>Palanisamy, R.</dc:creator>
	<dc:creator>Vidyasagar, S.</dc:creator>
	<dc:creator>Kalyanasundaram, V.</dc:creator>
	<dc:creator>Karthikeyan, D.</dc:creator>
	<dc:creator>Selvakumar, K.</dc:creator>
	<dc:creator>Selvabharathi, D.</dc:creator>
	<dc:creator>Vijayakumar, K.</dc:creator>
	<dc:description xml:lang="en-US">Multilevel converters have a significant role in power processing control in the power system, which has some inherent features like reduced harmonics, high power &amp;amp; medium voltage, reduced voltage stress. In this proposed paper, a novel multilevel inverter with reduced number of switches and without passive components. The proposed inverter generates 15 level output voltage with suitable switching pulse generation using multicarrier sinusoidal pulse width modulation (MSPWM) and different level of voltages are obtained with variation of modulation index. Also coupled inductor is used to minimize the harmonic content and smoothing output current. The scheme which includes different range of unequal voltage sources. As a result, the proposed system it reduces switching control complexity and there is no voltage balancing problem. This paper elucidates the operating modes, voltage stress minimisation and harmonic reduction are discussed. The results of the proposed multilevel dc-ac converter are verified using matlab/simulink. The simulation &amp;amp; hardware results of the proposed inverter were verified using matlab simulink and dsPIC controller respectively, which was analysed with different voltage level and different modulation index.</dc:description>
	<dc:publisher xml:lang="en-US">Institute of Advanced Engineering and Science</dc:publisher>
	<dc:contributor xml:lang="en-US"></dc:contributor>
	<dc:date>2020-06-01</dc:date>
	<dc:type>info:eu-repo/semantics/article</dc:type>
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	<dc:identifier>https://ijpeds.iaescore.com/index.php/IJPEDS/article/view/20416</dc:identifier>
	<dc:identifier>10.11591/ijpeds.v11.i2.pp752-761</dc:identifier>
	<dc:source xml:lang="en-US">International Journal of Power Electronics and Drive Systems (IJPEDS); Vol 11, No 2: June 2020; 752-761</dc:source>
	<dc:source>2722-256X</dc:source>
	<dc:source>2088-8694</dc:source>
	<dc:source>10.11591/ijpeds.v11.i2</dc:source>
	<dc:language>eng</dc:language>
	<dc:relation>https://ijpeds.iaescore.com/index.php/IJPEDS/article/view/20416/13084</dc:relation>
	<dc:rights xml:lang="en-US">Copyright (c) 2020 R. Palanisamy, S. Vidyasagar, V. Kalyanasundaram, D. Karthikeyan, K. Selvakumar, D. Selvabharathi, K. Vijayakumar</dc:rights>
	<dc:rights xml:lang="en-US">http://creativecommons.org/licenses/by-sa/4.0</dc:rights>
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