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The impact of channel fin width on electrical characteristics of Si-FinFET

International Journal of Electrical and Computer Engineering (IJECE) · Vol. 12 No. 1 (2022)

DOI
10.11591/ijece.v12i1.pp201-207
ISSN
2722-2578, 2088-8708
Published
2022-02-01
Publisher
Institute of Advanced Engineering and Science
License
creativecommons.org/licenses/by-sa/4.0

Abstract

This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W F =5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.

Collaboration network of the authors

13 authors · 23 co-authorship links · 6 across different organisations

Hover or tap a name to highlight its co-authors. Double-click to open the author's page.

  • Tishk International University
  • Universiti Malaysia Pahang Al-Sultan Abdullah
  • University of Mosul
  • Affiliation unknown
  • Different organisations
  • Same organisation
  • Affiliation unknown
  • Thicker line = more joint articles · bigger circle = more articles
Show as table
Co-authorOrganisationJoint articles
Waheb A. JabbarUniversiti Malaysia Pahang Al-Sultan Abdullah4
Ahmed MahmoodUniversiti Malaysia Pahang Al-Sultan Abdullah1
Hadi ManapUniversiti Malaysia Pahang Al-Sultan Abdullah1
Firas Natheer Abdul-kadirUniversity of Mosul1
Muhammad Nazmus ShakibAffiliation unknown1
Faris Hassan TahaUniversity of Mosul1
Hussein Mohammed AliTishk International University1
Ghadah A. Al-SakkalTishk International University1
Marwa AwniTishk International University1
Abdullah MufeedTishk International University1

Affiliations come from OpenAlex; journal OAI-PMH metadata carries none. Authors without an OpenAlex ID are matched by name, which can merge or split people.

This record comes from Crossref (what the publisher deposited), because the journal's own OAI-PMH endpoint could not be harvested.

Metadata source: Crossref API (cadangan, berdasarkan ISSN) https://api.crossref.org/journals/2088-8708/works, first harvested 27 Okt 2026, last seen 27 Okt 2026.
Metadata as oai_dc, converted from Crossref
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"><dc:title>The impact of channel fin width on electrical characteristics of Si-FinFET</dc:title><dc:creator>Atalla, Yousif</dc:creator><dc:creator>Hashim, Yasir</dc:creator><dc:creator>Abd. Ghafar, Abdul Nasir</dc:creator><dc:description>&lt;jats:p&gt;&amp;lt;span&amp;gt;This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W&amp;lt;sub&amp;gt;F&amp;lt;/sub&amp;gt;=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.&amp;lt;/span&amp;gt;&lt;/jats:p&gt;</dc:description><dc:publisher>Institute of Advanced Engineering and Science</dc:publisher><dc:date>2022-02-01</dc:date><dc:type>info:eu-repo/semantics/article</dc:type><dc:format>application/pdf</dc:format><dc:identifier>https://doi.org/10.11591/ijece.v12i1.pp201-207</dc:identifier><dc:identifier>10.11591/ijece.v12i1.pp201-207</dc:identifier><dc:source>International Journal of Electrical and Computer Engineering (IJECE); Vol 12 No 1 (2022); 201</dc:source><dc:source>2722-2578</dc:source><dc:source>2088-8708</dc:source><dc:relation>http://ijece.iaescore.com/index.php/IJECE/article/viewFile/24038/15423</dc:relation><dc:rights>http://creativecommons.org/licenses/by-sa/4.0</dc:rights></oai_dc:dc>